
// ****************************************************************************
//
//                         Page CH - charge meter
//
// ****************************************************************************
// I input: PD5, ADC5, input resistor: 1ohm/2W, input range 0..1A, minimal measured current 1mA, relative error 5%, absolute error 3mA
// ADC clock divider is set to 750kHz. One ADC clock cycle is 1.33us.
// I sampling time is (6) 71.5 cycles. One sample is 71.5+12.5=84 ADC clock cycles = 112us.

#ifndef _PAGE_CH_H
#define _PAGE_CH_H

#ifdef __cplusplus
extern "C" {
#endif

// Page CH (returns key PREV/NEXT)
u8 PageCH();

#ifdef __cplusplus
}
#endif

#endif // _PAGE_CH_H
